Design of a 4.2-5.4 GHz Differential LC VCO using 0.35 m SiGe BiCMOS Technology

In this paper, a 4.2-5.4 GHz, Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35´m SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). Phase noise is -110.7 dBc/Hz at 1MHz offset from 5.4 GHz carrier frequency and -113.5 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained utilizing accumulation-mode varactors. Phase noise is relatively low due to taking the advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. The circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit occupies an area of 0.6 mm2 on Si substrate including RF and DC pads

A study on dielectric properties of a new polyimide film suitable for interlayer dielectric material in microelectronics applications

Interlayer dielectric film formation under Al wirings for VLSI and ULSI devices requires low temperature processing and high surface planarization capability, Polymers as a dielectric material play a significant role in achieving the current state-of-the art in microelectronics. In this work, the dielectric properties of a new polyimide material suitable for microelectronics applications have been investigated. The polyimide was synthesized following the synthesis of 4,4'-bis(3-aminophenoxy)diphenyl sulfone (DAPDS), by nucleophilic aromatic substitution of 4,4'-dichlorodiphenyl sulfone with m-aminophenol, DAPDS/pyromellitic dianhydride (PMDA). Using this specific polyimide, a metal-polyimide-silicon (MIS) structure was manufactured to demonstrate the dielectric properties of the material. The properties of the MIS capacitance have been examined by deriving an electrical model of the MIS structure. (C) 2000 Published by Elsevier Science Ltd

Circuit Model for Statistical Method Based Reliability Estimation of MOS Transistors and Analog CMOS Circuits

Modern CMOS technologies are continuously scaling down. As a result of this, analog designers have serious reliability problems in their designs caused by physical effects such as hot carrier injection, negative and positive bias temperature instability (N/PBTI) and temperature dependent dielectric breakdown (TDDB). Therefore, it is an important factor estimating the deviations caused by these degradation mechanisms for a robust design. Note that the reliability of CMOS structures are considered for more than 40 years. Several works have been performed on these degradation effects in MOS structures and appeared in the literature. In most of the reliability studies available in the literature, physical models were proposed. However, difficulties in preparation of physical models seem to be the most important disadvantages of these type models. To overcome these disadvantages of physical models, statistical methods based on observation of experimental results have been introduced in some works. In this talk, statistical methods for modelling of the degradation caused deviations in the drain current and threshold voltage of the N-MOS and PMOS transistors are reviewed. [Note that these models are based on the observations by operating the device under stress voltage conditions. Using these observation results the effect of degradation was investigated statistically and a new statistical method was introduced to be an alternative to those given in the literature. The observed and the estimated values of the degradation are compared. The models introduced are independent of the realization technology and exhibit short simulation time and high accuracy. All data in this review is taken from the recent research works performed in Istanbul University and Istanbul Technical University